The present invention relates to a multistaged amplification circuit. In particular, it is suitable for use for multistaged amplification circuits commonly having a constant current source for bias at each stage.
Generally speaking, electronics devices receiving and processing an RF (Radio Frequency) signal, such as a radio receiver, a cellular phone, a codeless phone, a television receiver, a car navigation system, or a game machine with communication functions, use a differential multistaged amplification circuit (for example, a limiter amplifier, etc.) that enables high gain by multistaged cascade connection of differential amplifiers, in order to regenerate a received small input signal as a square wave.
There are two types of multistaged amplification circuit: one is a multistaged amplification circuit that individually connects a constant current source for a bias to a differential amplifier at each stage, and the other is a multistaged amplification circuit that commonly connects one constant current source to a differential amplifier at each stage. The constant current source is of a larger scale than other components, and the current consumed is also greater. Therefore, when attempting miniaturization or reduction of current consumed, a multistaged amplification circuit that causes the constant current source to be held individually at each stage is not suitable. Thus, a multistaged amplification circuit that commonly connects the constant current source to each stage should be used.
FIG. 1 is a diagram to indicate the structure of a conventional limiter amplifier that commonly has a constant current source at each stage. As shown in FIG. 1, a limiter amplifier is composed of n differential amplifiers 1, 2, and 3 connected in a multistaged manner to the output side from the input side. Each differential amplifier 1, 2, and 3 is composed of differential pairs comprising two resistances Ri1 and Ri2 (i=1 to n) and two transistors Qi1 and Qi2 (i=1 to n), and transistors Qi (i=1 to n) switching between such differential pairs.
In the individual differential pairs, the mutual sources of two transistors Qi1 and Qi2 (i=1 to n) are commonly connected, and each drain of the transistor Qi (i=1 to n) is connected with such common sources. Additionally, the drains of the transistors Qi1 and Qi2 (i=1 to n) are commonly connected with power VDD, via the resistances Ri1 and Ri2.
Also, output signals Vouti (i=1 to n−1) from differential amplifiers at previous stages are inputted to the gates of each transistors Qi1 and Qi2 except for a differential amplifier 1 at the initial stage. An input signal Vin is inputted to the gates of each transistor Q11 and Q12 of the differential amplifier 1 at the initial stage.
The source of each transistor Qi is commonly grounded via a ground line 5. Additionally, the gate of each transistor Qi is connected to the constant current source 4. Furthermore, the gate of transistor Q1 is connected to the constant current source 4. And such transistor Q1 and each transistor Qi are connected by a current mirror.
In the structured limiter amplifier mentioned above, the signal Vin inputted to the transistors Q11 and Q12 of the differential amplifier 1 at the initial stage is amplified only at a predominated level and outputted. In this circuit, the transistor 11 is outputted in an antiphase manner, and the transistor Q12 is outputted in phase in a common mode manner. The signal Vout1 amplified and outputted here is inputted to each base of transistors Q21 and Q22 of a differential amplifier 2 at the second stage, further amplified and outputted to in the differential amplifier 2.
The same applies hereinafter. That is to say, the signal is amplified in sequence by the differential amplifiers 1, 2, and 3 at each stage. Due to this, the amplitude of the input signal Vin to the differential amplifier 1 at the initial stage becomes larger as it reaches subsequent stages. And the output signal Vout amplified to a predominated level is ultimately obtained.
In the multistaged amplification circuit where a plurality of differential amplifiers are connected in a multistaged manner, when the constant current source is prepared commonly at each stage, such constant current source is normally arranged on the input side or the output side of the multistaged amplification circuit. Thus, for example, when the current constant source 4 is arranged on the input side as in FIG. 1, the wire length of the ground line 5 from the constant current source 4 to the differential amplifiers 1, 2, and 3 becomes longer as it goes to the subsequent stages.
Furthermore, the transistors Qi of each differential amplifier 1, 2, and 3 are grounded through the common ground line 5. Thus, distributed resistance, which becomes larger when going to subsequent stages, occurs on such ground line 5. Due to such distributed resistance, a voltage drop occurs, which becomes larger when going to subsequent stages, the ground level of each transistor Qi is not equal, and the balance of the current mirror is broken. Therefore, an appropriate amount of current cannot be supplied to the differential amplifiers 1, 2, and 3 at each stage in a well-balanced manner, and linearity with good input and output characteristics of the limiter amplifier cannot be preserved.
Also, when the multistaged amplification circuit, such as the limiter amplifier, operates in the high frequency area, and the wiring length becomes longer, the operation becomes accordingly unstable. Simultaneously, noise is easily superposed on the RF signal. The present invention has been made in order to resolve such difficulties. The purpose of the present invention is to preserve the good linearity of the differential amplifiers in a multistaged amplification circuit where differential amplifiers are connected in a multistaged manner, and to realize stability of operations and reduction of noise.